SUCCESS STORIES

Combining world-class expertise with leading-edge equipment

NANIUM’s history is full of enriching experiences in which we partnered with customers to develop good ideas into great solutions. Successes such as these require a unique combination of technology skills and infrastructure capabilities, together with innovative thinking and a dedicated team. These are the kind of challenges we enjoy.

Our team’s know-how and our high-volume manufacturing experience – with industrialization always in mind – set us apart as a company that realizes our customers’ ideas and concepts.

  

 

2015

 

LAUNCHED EWLB-BASED 10 CHIP ARRAY IN THE MEDICAL MARKET

In January 2015, we presented a solution that integrated 10 dies side-by-side in a 2 x 5 array. Featuring an outer package dimension of 33 x 28 mm2, this Wafer-Level Multi-Chip Module fully relied on the Fan-Out/eWLB technology that is our hallmark. The solution leveraged the eWLB processing capability in standard wafer-level equipment, successfully balancing dielectric and mold compound stress to create an extremely flat module. The final unit is incorporated within an ultra-compact medical device for visualizing vasculature and guiding peripheral intravenous access. 

See press release

  

 

2014

 

THE WORLD'S LARGEST FAN-IN / WLCSP

We were requested to deliver a customized Fan-In Wafer-Level Packaging/ WLCSP solution beyond common practice, as it was nine times larger in area compared to standard WLCSPs. We accept the challenge, and soon released an ASIC whose final units measure 25mm x 23mm. This final package solution is unprecedented by several times in thermal and computational performance, and it was produced on 300mm wafers, a packaging solution with proven manufacturability that was entirely developed in-house.

See press release

 

PRIOR TO 2014

 

IMPROVED DIELECTRIC MATERIAL

In late 2013, we launched an improved dielectric material and process solution for our fan-out wafer-level packaging (FOWLP) technology, embedded wafer-level ball grid array (eWLB). The applied improvements increased eWLB’s reliability, thereby extending our technology platform into more demanding markets and applications.
See press release.

 

MULTICHIP PACKAGING

Helping a Customer Realize New IP
The work required a customized high-performance FBGA package for DRAM to be mounted on modules for servers in data centers, and in mobile applications such as solder-down memory for UltraBooks™ and tablets. The result had to be smaller and thinner than conventional FBGA package solutions, enable multi-chip scaling in a chip-scale package form factor, include low-risk and low-cost technology in an existing manufacturing environment and deliver better electrical and thermal performance.
This required modification and customization of a conventional organic laminated substrate-based FBGA with one bond channel (Window-BGA) for a high-performance package. Many years of high-volume production of a large number of different memory products in different FBGA variants have made NANIUM a specialist in this field.


A Strategy for Competing with More Expensive Solutions

The customer’s new package-construction concept was key to the solution. Applying mature wire-bond and transfer molding technology capable of high volume and yields, NANIUM industrialized the concept, which is key to the customer’s strategy for competing with existing, more expensive and lower-performing multi-die package solutions, such as through-silicon via (TSV) products.

The project maximized our proven capabilities, including:
· packaging and assembly of FBGA (Window-BGA) in high volume
· test and test-program development for DRAM products
· process and material understanding and process-integration experience
· design for manufacturability and design for reliability know-how, and
· extensive in-house reliability test-and-failure analysis capabilities


The customer’s concept had to be verified by joint package design and simulation work. Having packaging, assembly and test know-how under one roof was a strong advantage that enabled the continuous interaction and close cooperation between our team and the customer. In addition to executing the engineering work requested, NANIUM engineers continuously provided feedback and suggestions that often lead to improvements of the concept.


High Volume, High Yield, Low Risk

Because of this collaboration, an FBGA multi-die package solution was developed with proven high electrical and thermal performance. It can be produced in high volume with low risk and high yield on existing assembly lines. The project also met performance parameters of a DRAM, packaged in a single-die package, with two dies, resulting in double capacity, which impacts the performance of the DRAM significantly.

This was done by interconnecting both single dies monolithically to the outside of the package, while they are physically integrated in one package. We also developed an FBGA package with larger ball-out and two bond channels, and we improved production test yields due to symmetric die performance. In addition, we achieved speed yield gain and better heat dissipation than conventional stacked dual-die packages.

 

  

EMBEDDED WAFER LEVEL BALL GRID ARRAY

Good engineering requires a complex, interactive combination of technical capabilities, creativity, communication and innovative thinking.

eWLB Gives Package 30 Percent Size Reduction, With Better Thermal and Electrical Performance
An excellent example is a recent NANIUM partnership with a producer of extremely sensitive measurement equipment. The customer’s compact new-generation system will utilize a broadband RF ASIC device operating at frequencies in excess of 10GHz, built on a very small die and facing stringent electrical and thermal performance standards. Existing packaging options simply didn’t work because of size and performance limitations. Solving this challenge required a wide range of engineering disciplines from across NANIUM, and also extensive teamwork involving the customer’s system and application-engineering teams, as well as their chip designers.

30 Percent Form-Factor Reduction
This adaptation was complex, but the advantages were clear. eWLB allowed for a very flexible and fully customizable fan-out zone, while offering full access to the die’s backside. It required no substrate or interposer, no wire bonds, and very short electrical connections, all of which combined to provide superior electrical and thermal performance compared to conventional substrate-based BGA and flip-chip-in-package (FCiP) approaches. The resulting package had a form factor 30 percent smaller than other options, and incorporated novel heat-management techniques. Best of all, NANIUM’s integrated knowledge and solution-oriented approach meant the effort was able to go from project start to qualification in just eight months – a record that led the customer to sign up for additional development projects.
See press release.