WAFER-LEVEL PACKAGING

World-class development, manufacturing, testing and engineering for semiconductor innovators

Wafer-level packaging (WLP) is a key technology in the semiconductor industry, mainly when produced in 300mm carriers, because of the performance and cost advantages it delivers for smartphones, tablets and other applications that require high functionality and low power consumption in a small form factor.

NANIUM has extensive experience in high-volume manufacturing and processing of 300mm wafers / carriers along with fully qualified production assembly capability. We offer a wide range of wafer-level processing, including dicing and grinding, bumping and wafer-level packaging, supported by world-class metrology methods and automated defect inspection systems.

NANIUM is a global leader in high-volume embedded wafer-level fan-out (WLFO) technology and our service portfolio also includes wafer-level chip scale packaging (WLCSP). With the combination of our 300mm fan-in and fan-out WLP technologies, NANIUM offers a one-stop shop solution to our customers through a wide range of product solutions and process options.

 

WAFER-LEVEL FAN-OUT

WLFO's benefits include the flexibility to enable 3D multi-component package designs (WL3D); its outstanding performance at mechanical, electrical and thermal level; and its smaller, thinner and lighter package, as WLFO allows for the highest integration density commercially available in the industry.

 

NANIUM is a world leader in Wafer-Level Fan-Out, the fastest-growing packaging technology, and one of the advanced packaging platforms that is the most promising. The interest sparked by WLFO stems from all the strong benefits it offers, which are particularly appealing to markets with small-form factor needs, tight transmission loss requirements or high performance demands.

 

WLFO enables flexible System-in-Package (WLSiP) and heterogeneous integration (WL3D) packaging solutions. Its superior electrical and thermal performance is due to shorter and more precise interconnections, as well as reduced material layers, which are specially recommended for very high frequency applications.

With our proven high-volume manufacturing capability, we have shipped over 900 million WLFO packages, achieving industry-level yields and full JEDEC quality/reliability compliance. WLFO is a RoHS- and REACH-compliant packaging technology.

For more on WLFO, check our datasheet on Fan-Out Wafer-Level Package.


WAFER-LEVEL CHIP SCALE PACKAGE

NANIUM provides solutions for 300mm WLCSP based on fan-in WLP processes, a technology that allows packages covering a wide range of die sizes, bump height/pitch and Si-die thickness. Even though it is still a young player in the WLCSP arena, NANIUM has already demonstrated clear competitiveness, often leveraged by the company’s proficiency in Wafer-Level Fan-Out (WLFO) technology. Shortly after entering the WLCSP market, NANIUM launched innovative packaging solutions, and currently offers qualified WLCSP sizes up to 23x25mm2  (the largest in the market), packages with 2 RDL layers with or without UBM, as well as low temperature processing.

 

Wafer-Level Chip Scale Packages (WLCSP) enable low-cost manufacturing, with low to medium I/O density and high performance. The technology includes repassivation, redistribution (RDL), under bump metallization (UBM), bumping, test, laser marking, singulation, automatic inspection (AOI) and pick & pack in tape & reel.

WLCSP product applications include Mobile and Consumer Products; Wireless Connectivity including Bluetooth, WLAN, RF, FM radio, GPS; PMIC, PMU, High Performance Computing; Analog and other ICs like MEMS and Sensors.

For more on WLCSP, check our datasheet on Wafer-Level Chip-Scale Package.


WLCSP+

NANIUM offers an advanced packaging solution, attained through a fusion of its leading-edge WLFO technology knowledge and HVM capabilities with classical WLCSP technology. In essence, the package applies a thin mold compound layer over the die’s backside and sidewall, offering an additional 5-side mechanical protection, as well as superior product robustness for handling.

 

WLCSP+ allows for WLCSP products to be processed in large format 300mm reconstituted wafer format independently of the incoming wafer size. The Known-Good Dies (KGD) of the grinded and diced incoming wafers are placed together in a new, standardized, 300mm reconstituted mold wafer with very short distance between each other. As redistribution routing and bumps are placed on the die itself only, it remains a WLCSP solution. However, it relies on a reconstituted mold wafer. In this way, for instance, dies from two 200mm wafer, or from even more wafers with smaller diameters, can be processed on one reconstituted 300mm mold wafer. This translates into cost advantage, which may be amplified in accordance with the incoming wafer’s diameter, die size and yield.

Another advantage of this concept is that the wafer probe can be applied to already singulated dies, embedded in the reconstituted moldwafer in order to test for dicing fails. Before WLCSP+, this was only possible through expensive bare die testing. 


For more on WLCSP+, check our datasheet on WLCSP+ or read the WLCSP+ press release.


CUSTOMIZED WAFER-LEVEL SERVICES

NANIUM's world-class services are always tailored to our customers’ needs. In this way, the WL solutions we provide range from single- to multi-die, system-in-package and package-on-package with passives integration.

Tailoring prime solutions, however, requires a deep understanding of the market preposition. That is why we always develop our package solutions in close collaboration with our customers, sometimes cooperating from the earliest stage of the Silicon chip development (co-design), others co-developing complex packaging solutions (for example: Wafer-Level-based System-in-Package) or customized test solutions.